As the size and speed of silicon devices shrink current leakage and other reliability problems increase. In flash memories, fast program/erase times and operating voltage reductions are the primary issues facing the continued development of improved devices. With a given budget for operating voltages the main option for the device designer is a trade-off between low power and high speed. The operating voltage scales with device dimensions which are relatively fixed for the current generation of technology. Thus the most promising option left for device improvement is to increase the coupling ratio by increasing the floating gate capacitance.
The main options for increasing the floating gate capacitance are to reduce the intergate dielectric thickness or to alter the dielectric properties of the intergate dielectric material. Device and process designers to date have recognized that as the intergate dielectric thickness shrinks, the potential for leakage and other electrical defects increases. Thus the quality of the dielectric material used is important. The highest quality material so far developed in silicon technology for low defects and for low surface state density is SiO.sub.2. An important advantage of SiO.sub.2 is that it can be grown from the underlying poly gate. It is well known that grown oxides tend to have fewer defects, e.g. pinholes, than deposited materials. Thus SiO.sub.2 has persisted as the dielectric material of choice in most silicon device structures.
In spite of the popularity of SiO.sub.2 as a dielectric material, some efforts to increase floating gate capacitance have focused on newly developed dielectric materials. The use of Ta.sub.2 O.sub.5 as a dielectric has been proposed for MOSFETs (see Youichi Momiyama et al, "Ultra-Thin Ta.sub.2 O.sub.5 /SiO.sub.2 Gate Insulator with TiN Gate Technology for 0.1 .mu.m MOSFETs", 1997 Symposium on VLSI Technology Digest of Technical Papers, pp. 135,136. This material has also been proposed for stacked and trench capacitors in DRAM structures (see Tomonori Aoyama et al, "Leakage Current Mechansim of Amorphous and Polycrystalline Ta.sub.2 O.sub.5 Films Grown by Chemical Vapor Deposition", J. Electrochem. Soc., Vol. 143, No. 3, pp. 977-983, March 1996.
Efforts to develop new dielectric materials for flash memories have also been reported. See e.g. W-H Lee et al, "A Novel High K Inter-Poly Dielectric (IPD), Al.sub.2 O.sub.3 for Low Voltage/High Speed Flash Memories: Erasing in msecs at 3.3V", 1997 Symposium on VLSI Technology Digest of Technical Papers, pp. 117,118. The essence of this proposal is to substitute Al.sub.2 O.sub.3 for SiO.sub.2 as the dielectric between the control gate of the flash memory and the floating gate. Alumina has a dielectric constant approximately twice that of the widely used SiO.sub.2 dielectric, thus giving substantial improvement in the capacitance between the polysilicon control gate and the polysilicon floating gate.
While many of these new proposals show promise, a growing issue in these devices is the quality of the dielectric interfaces in multi-layer structures. As the dimensions of storage devices shrinks, and the operating power levels are reduced, the amount of electrical charge that represents a one or zero in a binary bit stream declines as well. With a relatively small number of charges distinguishing between data bit states, a significant loss of charge through recombination at interface defects can reduce the signal to noise ratio of the device to unacceptable margins. Thus while modification of the dielectric composition of interlevel gate dielectrics theoretically achieves new benefits, in practice the processing used to form these new structures is important in realizing the theoretical advantages.